This application claims the priority of Korean Patent Application No. 2003-75815, filed on Oct. 29, 2003, in the Korean Intellectual Property Office, the contents of which are incorporated herein in their entirety by reference.
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a method of writing data into a memory cell with a boosted bitline voltage, which is higher than a power supply voltage, and a memory device that performs the method.
2. Description of the Related Art
A dynamic random access memory (DRAM) includes memory cells, and each of the memory cells is comprised of a transistor and a capacitor. Each of the memory cells, i.e., DRAM cells, stores a logic data value of “1” or “0” according to the amount of electric charge stored in its memory cell capacitor. In general, a data value of 1 is stored in a DRAM cell with a power supply voltage level (VCC), and a data value of 0 is stored in a DRAM cell with a ground voltage level (VSS). Due to the characteristics of a DRAM cell, electric charge leaks from a capacitor of the DRAM cell, and thus a voltage level of data stored in the capacitor of the DRAM cell gradually decreases. Given such electric charge leakage, a data value of 1 is preferably stored with a higher voltage level than the power supply voltage level VCC.
Data stored in each DRAM cell is charge-shared between bitlines, and then is sensed and amplified by a bitline sense amplifier. The larger the difference between the amount of electric charge in a cell capacitor holding a data value of 1, and the amount of electric charge of a cell capacitor holding a data value of 0, the higher the efficiency of the bitline sense amplifier sensing data stored in each of the cell capacitors. The amount of electric charge stored in each of the cell capacitors can be increased by increasing the capacitance of each of the cell capacitors. However, since there are numerous restrictions placed on increasing the size of a chip or manufacturing a semiconductor device, there is a clear limit as to the amount by which the capacitance of each of the cell capacitors can be increased.
Therefore, in order to achieve a high sensing efficiency with a given amount of electric charge stored in a cell capacitor with a predetermined capacitance, the voltage of bitlines can be increased after the electric charge stored in the cell capacitor is shared between the bitlines, by decreasing capacitance of each of the bitlines. Alternatively, the bitline voltage can be increased during a sensing process by increasing the amount of electric charge stored in the cell capacitor.
However, if a data value of 1 is written into a DRAM cell capacitor by charging the DRAM cell capacitor with a higher voltage level than the power supply voltage level (VCC), the amount of electric charge stored in the DRAM cell capacitor increases.